Trysne Project Status (08/13/2008 - 18:35:05)
Project File:	Trysne.ise	Current State:	Programming File Generated
Module Name:	testsine	Errors:	No Errors
Target Device:	xc3s500e-4fg320	Warnings:	27 Warnings
Product Version:	ISE 10.1.02 - WebPACK	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Timing Report)

 

Trysne Partition Summary				[-]
No partition information was found.

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	124	9,312	1%
Number of 4 input LUTs	190	9,312	2%
Logic Distribution
Number of occupied Slices	144	4,656	3%
Number of Slices containing only related logic	144	144	100%
Number of Slices containing unrelated logic	0	144	0%
Total Number of 4 input LUTs	213	9,312	2%
Number used as logic	154
Number used as a route-thru	23
Number used as Shift registers	36
Number of bonded IOBs
Number of bonded	11	232	4%
Number of RAMB16s	14	20	70%
Number of BUFGMUXs	1	24	4%
Number of DCMs	1	4	25%
Number of MULT18X18SIOs	1	20	5%
Number of RPM macros	12

 

Performance Summary				[-]
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	wo 13. aug 18:31:38 2008	0	19 Warnings	1 Info
Translation Report	Current	wo 13. aug 18:32:26 2008	0	6 Warnings	0
Map Report	Current	wo 13. aug 18:32:59 2008	0	2 Warnings	3 Infos
Place and Route Report	Current	wo 13. aug 18:34:15 2008	0	0	1 Info
Static Timing Report	Current	wo 13. aug 18:34:40 2008	0	0	2 Infos
Bitgen Report	Current	wo 13. aug 18:35:01 2008	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
Xplorer Report

Date Generated: 08/13/2008 - 18:35:06