Theo Verelst SIGGRAPH 2006 page

© Theo Verelst, theover@tiscali.nl, free non-commercial use permitted, when author is mentioned in derived works.

           

This page will contain my paper, files and pictures related to
 .

I've made a start with a bezier surface based graphics processor and DSP system and interface, which is already in working prototype phase, although I didn't yet think of a type of application I'll make with the system.

First, the design files, zipped per project for the Xilinx Spartan 3 Demo board (the 200 one) and Analog Devices Blackfin Dual Core 561 DSP, and then the bezier subdivision test C program and an example bezier model.













Well, I'll get the rebuttals from the siggraph site some day too, but for the moment, the comments were serious, langauge style and various content issues were completely contradictory (just ok to very good, rediculous pityfull comments to denial of the importance of the subject (jeez) and some stuff I look up and possibly post here), just one issue was shared amoung 5 reviewers: the experiment was well documented and cinsidered very repeatable and though to be in line with advanced graduation subject issues. But NOT a fundamental issue, and especially complete failure of correctness and relevance estimation has occurred with respect to benchmarks, which were in the document, which isn't accepted, which is overcomable since I spent two weeks on the preparation of the text and the experiment.

To see what an actual implementation has as resource use :

Project File: Bezier.ise Current State: Programming File Generated
Module Name: topbez45
  • Errors:
 No Errors
Target Device: xc3s200-4ft256
  • Warnings:
 250 Warnings (0 new)
Product Version: ISE 8.2.03i
  • Updated:
 di 5. aug 15:58:25 2008
 
BEZIER Partition Summary
No partition information was found.
 
Device Utilization Summary
Logic Utilization Used Available Utilization Note(s)
Total Number Slice Registers 215 3,840 5%  
    Number used as Flip Flops 119      
    Number used as Latches 96      
Number of 4 input LUTs 3,385 3,840 88%  
Logic Distribution        
Number of occupied Slices 1,918 1,920 99%  
    Number of Slices containing only related logic 1,833 1,918 95%  
    Number of Slices containing unrelated logic 85 1,918 4%  
Total Number 4 input LUTs 3,429 3,840 89%  
Number used as logic 3,385      
Number used as a route-thru 8      
Number used as Shift registers 36      
Number of bonded IOBs 110 173 63%  
    IOB Flip Flops 38      
    IOB Latches 32      
Number of Block RAMs 1 12 8%  
Number of GCLKs 5 8 62%  
Number of RPM macros 114      
Total equivalent gate count for design 100,144      
Additional JTAG gate count for IOBs 5,280      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report Name Status Generated Errors Warnings Infos
Synthesis Report Current di 5. aug 15:56:58 2008 0 220 Warnings (0 new) 1 Info (0 new)
Translation Report Current di 5. aug 15:57:16 2008 0 3 Warnings (0 new) 0
Map Report Current di 5. aug 15:57:36 2008 0 22 Warnings (0 new) 2 Infos (0 new)
Place and Route Report Current di 5. aug 15:58:06 2008 0 1 Warning (0 new) 2 Infos (0 new)
Static Timing Report Current di 5. aug 15:58:14 2008 0 0 2 Infos (0 new)
Bitgen Report Current di 5. aug 15:58:26 2008 0 4 Warnings (0 new) 0



You can see the article here (pdf format) for viewing, not for reproduction in any form, copyright T. Verelst.