library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity display1 is
    Port ( hex : in std_logic_vector(3 downto 0);
           segments : out std_logic_vector(6 downto 0));
end display1;

architecture Behavioral of display1 is
begin
    with hex SELect
   segments <= "0000011" when "0001",   --1
         "1101101" when "0010",   --2
         "1100111" when "0011",   --3
         "1010011" when "0100",   --4
         "1110110" when "0101",   --5
         "1111110" when "0110",   --6
         "0100011" when "0111",   --7
         "1111111" when "1000",   --8
         "1110011" when "1001",   --9
         "1111011" when "1010",   --A
         "1011110" when "1011",   --b
         "0111100" when "1100",   --C
         "1001111" when "1101",   --d
         "1111100" when "1110",   --E
         "1111000" when "1111",   --F
         "0111111" when others;   --0
 



end Behavioral;