cpldfit: version H.42 Xilinx Inc. Fitter Report Design Name: top2 Date: 12-25-2005, 9:10PM Device Used: XC2C256-7-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 76 /256 ( 30%) 143 /896 ( 16%) 125 /640 ( 20%) 59 /256 ( 23%) 49 /118 ( 42%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO CTC CTR CTS CTE Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot FB1 16/16* 17/40 37/56 3/ 6 1/1* 1/1* 0/1 0/1 FB2 16/16* 21/40 23/56 4/ 8 1/1* 1/1* 0/1 0/1 FB3 16/16* 19/40 22/56 3/ 6 1/1* 0/1 1/1* 0/1 FB4 12/16 19/40 23/56 6/ 8 1/1* 0/1 0/1 0/1 FB5 0/16 0/40 0/56 0/ 5 0/1 0/1 0/1 0/1 FB6 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB7 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB8 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB9 5/16 19/40 16/56 5/ 8 0/1 0/1 0/1 1/1* FB10 0/16 0/40 0/56 0/ 9 0/1 0/1 0/1 0/1 FB11 5/16 21/40 15/56 4/ 8 1/1* 0/1 0/1 1/1* FB12 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1 FB13 2/16 2/40 2/56 2/ 8 1/1* 0/1 0/1 0/1 FB14 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB15 4/16 7/40 5/56 4/ 7 1/1* 0/1 0/1 0/1 FB16 0/16 0/40 0/56 0/ 7 0/1 0/1 0/1 0/1 ----- ------- ------- ----- --- --- --- --- Total 76/256 125/640 143/896 31/118 7/16 2/16 1/16 2/16 CTC - Control Term Clock CTR - Control Term Reset CTS - Control Term Set CTE - Control Term Output Enable * - Resource is exhausted ** Global Control Resources ** GCK GSR GTS Used/Tot Used/Tot Used/Tot 1/3 0/1 0/4 Signal 'clock_in' mapped onto global clock net GCK2. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 17 17 | I/O : 44 108 Output : 23 23 | GCK/IO : 1 3 Bidirectional : 8 8 | GTS/IO : 4 4 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | CDR/IO : 0 1 GSR : 0 0 | DGE/IO : 0 1 ---- ---- Total 49 49 End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld:942 - A component 'XLXI_295' of type '???' is missing input(s) or output(s) and will be deleted. WARNING:Cpld:942 - A component 'XLXI_275' of type '???' is missing input(s) or output(s) and will be deleted. WARNING:Cpld:945 - The component 'XLXI_35' has no outputs and will be deleted. WARNING:Cpld:945 - The component 'XLXI_39' has no outputs and will be deleted. WARNING:Cpld:945 - The component 'XLXI_40' has no outputs and will be deleted. WARNING:Cpld:945 - The component 'XLXI_41' has no outputs and will be deleted. WARNING:Cpld:945 - The component 'XLXI_43' has no outputs and will be deleted. WARNING:Cpld:945 - The component 'XLXI_90' has no outputs and will be deleted. WARNING:Cpld:945 - The component 'XLXI_94' has no outputs and will be deleted. WARNING:Cpld:945 - The component 'XLXI_163' has no outputs and will be deleted. WARNING:Cpld:960 - PULLUP specified for net 'b' conflicts with previous KEEPER specification. PULLUP is ignored. WARNING:Cpld:960 - PULLUP specified for net 'a' conflicts with previous KEEPER specification. PULLUP is ignored. WARNING:Cpld:828 - Signal 'XLXN_1076.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXN_1072.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'hex<3>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'hex<2>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'hex<0>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'hex<1>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'Qa<9>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'Qa<8>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_32/Q<7>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_32/Q<6>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_32/Q<5>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_32/Q<4>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_32/Q<3>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_32/Q<2>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_32/Q<1>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_32/Q<0>.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_277/Q0.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_277/Q1.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_277/Q2.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:828 - Signal 'XLXI_277/Q3.CE' has been minimized to 'VCC'. The signal is removed. WARNING:Cpld:179 - The signal(s) 'qold' are in combinational feedback loops. These signals may cause hazards/glitches. Logic should include hazard reduction circuitry to avoid hazards/glitches. Apply the NOREDUCE parameter to the hazard reduction circuitry. ************************* Summary of Mapped Logic ************************ ** 31 Outputs ** Signal Total Total Loc Pin Pin Pin I/O I/O Slew Reg Reg Init Name Pts Inps No. Type Use STD Style Rate Use State lda 3 4 FB1_4 142 I/O O LVCMOS33 SLOW ldb 3 4 FB1_12 139 I/O O LVCMOS33 SLOW ldc 4 4 FB1_14 137 I/O O LVCMOS33 SLOW db7 2 4 FB2_12 6 GTS/I/O O LVCMOS33 FAST DFF RESET db6 2 4 FB2_13 7 I/O O LVCMOS33 FAST DFF RESET db5 2 4 FB2_14 9 I/O O LVCMOS33 FAST DFF RESET db4 2 4 FB2_15 10 I/O O LVCMOS33 FAST DFF RESET ldd 3 4 FB3_2 135 I/O O LVCMOS33 SLOW lde 3 4 FB3_5 133 I/O O LVCMOS33 SLOW ldf 3 4 FB3_16 131 I/O O LVCMOS33 SLOW db3 2 4 FB4_1 11 I/O O LVCMOS33 FAST DFF RESET db2 2 4 FB4_2 12 I/O O LVCMOS33 FAST DFF RESET db1 2 4 FB4_3 13 I/O O LVCMOS33 FAST DFF RESET db0 2 4 FB4_4 14 I/O O LVCMOS33 FAST DFF RESET e 2 4 FB4_5 15 I/O O LVCMOS33 FAST DFF RESET rs 2 4 FB4_6 16 I/O O LVCMOS33 FAST DFF RESET datab0 4 7 FB9_6 115 I/O I/O LVCMOS33 KPR FAST datab2 4 7 FB9_12 116 I/O I/O LVCMOS33 KPR FAST datab4 4 7 FB9_13 117 I/O I/O LVCMOS33 KPR FAST datab6 4 7 FB9_14 118 I/O I/O LVCMOS33 KPR FAST datab7 4 7 FB9_15 119 I/O I/O LVCMOS33 KPR FAST datab5 4 7 FB11_5 120 I/O I/O LVCMOS33 KPR FAST datab3 4 7 FB11_6 121 I/O I/O LVCMOS33 KPR FAST datab1 4 7 FB11_11 124 I/O I/O LVCMOS33 KPR FAST ldg 3 4 FB11_15 129 I/O O LVCMOS33 SLOW ll5 1 1 FB13_6 79 I/O O LVCMOS33 SLOW TFF/S SET ll4 1 1 FB13_13 81 I/O O LVCMOS33 SLOW TFF/S SET ll3 1 1 FB15_2 83 I/O O LVCMOS33 SLOW TFF/S SET ll2 1 1 FB15_12 86 I/O O LVCMOS33 SLOW TFF/S SET ll1 1 1 FB15_14 88 I/O O LVCMOS33 SLOW TFF/S SET boardled1 2 4 FB15_16 92 I/O O LVCMOS33 FAST DFF/S SET ** 45 Buried Nodes ** Signal Total Total Loc Reg Reg Init Name Pts Inps Use State XLXI_36/Q2 1 2 FB1_1 TFF RESET XLXI_36/Q1 1 1 FB1_2 TFF RESET XLXI_277/Q1 2 2 FB1_3 TFF RESET XLXI_36/Q0 0 0 FB1_5 TFF RESET qold 1 2 FB1_6 XLXN_281 2 2 FB1_7 DFF RESET XLXN_280 2 2 FB1_8 DFF RESET hex<0> 2 2 FB1_9 TFF RESET N_PZ_340 4 5 FB1_10 hex<1> 5 7 FB1_11 TFF RESET XLXN_244 1 3 FB1_13 TFF RESET hex<2> 7 8 FB1_15 TFF RESET hex<3> 7 9 FB1_16 TFF RESET XLXN_268 2 3 FB2_1 DFF RESET XLXI_287/Q2 3 9 FB2_2 TFF RESET XLXN_1018 3 7 FB2_3 DEFF RESET XLXN_287 1 1 FB2_4 DFF RESET XLXN_1061 3 10 FB2_5 TFF RESET XLXI_287/Q1 3 8 FB2_6 TFF RESET XLXN_1068 3 7 FB2_7 TFF RESET XLXN_1076 3 6 FB2_8 TFF RESET XLXN_1072 2 5 FB2_9 TFF RESET XLXI_277/Q0 2 5 FB2_10 TFF RESET XLXI_277/Q3 2 4 FB2_11 TFF RESET XLXI_277/Q2 2 3 FB2_16 TFF RESET XLXN_1041 2 3 FB3_1 DFF RESET XLXN_1049 2 2 FB3_3 TFF RESET Qa<9> 2 10 FB3_4 TFF RESET Qa<8> 2 9 FB3_6 TFF RESET XLXI_32/Q<7> 2 8 FB3_7 TFF RESET XLXI_32/Q<6> 2 7 FB3_8 TFF RESET XLXI_32/Q<5> 2 6 FB3_9 TFF RESET XLXI_32/Q<4> 2 5 FB3_10 TFF RESET XLXI_32/Q<3> 2 4 FB3_11 TFF RESET XLXI_32/Q<2> 2 3 FB3_12 TFF RESET XLXI_32/Q<1> 2 2 FB3_13 TFF RESET XLXN_1048 1 1 FB3_14 TFF RESET XLXI_32/Q<0> 1 1 FB3_15 TFF RESET XLXN_1029 3 7 FB4_9 DEFF RESET XLXN_1028 3 7 FB4_10 DEFF RESET Signal Total Total Loc Reg Reg Init Name Pts Inps Use State XLXN_1027 3 7 FB4_11 DEFF RESET XLXN_1022 3 7 FB4_13 DEFF RESET XLXN_1021 3 7 FB4_15 DEFF RESET XLXN_1020 3 7 FB4_16 DEFF RESET XLXN_929 2 6 FB11_14 DEFF RESET ** 18 Inputs ** Signal Loc Pin Pin Pin I/O I/O Name No. Type Use STD Style rotl FB2_1 2 GTS/I/O I LVCMOS33 a FB2_3 3 GTS/I/O I LVCMOS33 KPR rotr FB2_4 4 I/O I LVCMOS33 b FB2_5 5 GTS/I/O I LVCMOS33 KPR butr FB4_12 17 I/O I LVCMOS33 KPR butl FB4_14 18 I/O I LVCMOS33 KPR clock_in FB6_4 38 GCK/I/O GCK LVCMOS33 KPR NAMS3 FB9_1 112 I/O I LVCMOS33 KPR A2 FB9_2 113 I/O I LVCMOS33 KPR A1 FB9_4 114 I/O I LVCMOS33 KPR NAWE FB10_1 111 I/O I LVCMOS33 KPR NARE FB10_2 110 I/O I LVCMOS33 KPR midiin FB11_14 128 I/O I LVCMOS33 S/KPR bl5 FB13_5 78 I/O I LVCMOS33 KPR bl4 FB13_12 80 I/O I LVCMOS33 KPR bl3 FB13_14 82 I/O I LVCMOS33 KPR bl2 FB15_11 85 I/O I LVCMOS33 KPR bl1 FB15_13 87 I/O I LVCMOS33 KPR Legend: Pin No. - ~ - User Assigned I/O Style - OD - OpenDrain - PU - Pullup - KPR - Keeper - S - SchmittTrigger - DG - DataGate Reg Use - LATCH - Transparent latch - DFF - D-flip-flop - DEFF - D-flip-flop with clock enable - TFF - T-flip-flop - TDFF - Dual-edge-triggered T-flip-flop - DDFF - Dual-edge-triggered flip-flop - DDEFF - Dual-edge-triggered flip-flop with clock enable /S (after any above flop/latch type) indicates initial state is Set ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset VRF - Vref Pin No. - ~ - User Assigned *********************************** FB1 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 17/23 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 37/19 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use XLXI_36/Q2 1 FB1_1 (b) (b) XLXI_36/Q1 1 FB1_2 (b) (b) XLXI_277/Q1 2 FB1_3 143 GSR/I/O (b) lda 3 FB1_4 142 I/O O XLXI_36/Q0 0 FB1_5 (b) (b) qold 1 FB1_6 140 I/O (b) XLXN_281 2 FB1_7 (b) (b) XLXN_280 2 FB1_8 (b) (b) hex<0> 2 FB1_9 (b) (b) + + N_PZ_340 4 FB1_10 (b) (b) hex<1> 5 FB1_11 (b) (b) + + ldb 3 FB1_12 139 I/O O XLXN_244 1 FB1_13 138 I/O (b) ldc 4 FB1_14 137 I/O O hex<2> 7 FB1_15 (b) (b) + + hex<3> 7 FB1_16 (b) (b) + + Signals Used by Logic in Function Block 1: N_PZ_340 7: XLXN_1041 13: a 2: Qa<9> 8: XLXN_268 14: hex<0> 3: XLXI_277/Q0 9: XLXN_268.COMB 15: hex<1> 4: XLXI_36/Q0 10: XLXN_280 16: hex<2> 5: XLXI_36/Q1 11: XLXN_281 17: hex<3> 6: XLXI_36/Q2 12: XLXN_287 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs XLXI_36/Q2 ...XX................................... 2 XLXI_36/Q1 ...X.................................... 1 XLXI_277/Q1 ..X...X................................. 2 lda .............XXXX....................... 4 XLXI_36/Q0 ........................................ 0 qold ........X...X........................... 2 XLXN_281 .X.........X............................ 2 XLXN_280 .X.....X................................ 2 hex<0> X.......X............................... 2 N_PZ_340 .X.....X.XXX............................ 5 hex<1> X......XXXXX.X.......................... 7 ldb .............XXXX....................... 4 XLXN_244 ...XXX.................................. 3 ldc .............XXXX....................... 4 hex<2> X......XXXXX.XX......................... 8 hex<3> X......XXXXX.XXX........................ 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 21/19 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 23/33 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use XLXN_268 2 FB2_1 2 GTS/I/O I XLXI_287/Q2 3 FB2_2 (b) (b) + + XLXN_1018 3 FB2_3 3 GTS/I/O I + XLXN_287 1 FB2_4 4 I/O I XLXN_1061 3 FB2_5 5 GTS/I/O I + + XLXI_287/Q1 3 FB2_6 (b) (b) + + XLXN_1068 3 FB2_7 (b) (b) + + XLXN_1076 3 FB2_8 (b) (b) + + XLXN_1072 2 FB2_9 (b) (b) + + XLXI_277/Q0 2 FB2_10 (b) (b) + XLXI_277/Q3 2 FB2_11 (b) (b) + db7 2 FB2_12 6 GTS/I/O O db6 2 FB2_13 7 I/O O db5 2 FB2_14 9 I/O O db4 2 FB2_15 10 I/O O XLXI_277/Q2 2 FB2_16 (b) (b) + Signals Used by Logic in Function Block 1: A1 8: XLXI_277/Q3 15: XLXN_1076 2: NAMS3 9: XLXI_287/Q1 16: b 3: NAWE 10: XLXI_287/Q2 17: datab4.PIN 4: Qa<9> 11: XLXN_1029 18: datab5.PIN 5: XLXI_277/Q0 12: XLXN_1041 19: datab6.PIN 6: XLXI_277/Q1 13: XLXN_1068 20: datab7.PIN 7: XLXI_277/Q2 14: XLXN_1072 21: qold Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs XLXN_268 ...X...........X....X................... 3 XLXI_287/Q2 ....XXXXX..XXXX......................... 9 XLXN_1018 ....XXXX..X..XX......................... 7 XLXN_1061 ....XXXXXX.XXXX......................... 10 XLXI_287/Q1 ....XXXX...XXXX......................... 8 XLXN_1068 ....XXXX...X.XX......................... 7 XLXN_1076 ....XXXX...X.X.......................... 6 XLXN_1072 ....XXXX...X............................ 5 XLXI_277/Q0 ....XXXX...X............................ 5 XLXI_277/Q3 ....XXX....X............................ 4 db7 XXX................X.................... 4 db6 XXX...............X..................... 4 db5 XXX..............X...................... 4 db4 XXX.............X....................... 4 XLXI_277/Q2 ....XX.....X............................ 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 19/21 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 22/34 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use XLXN_1041 2 FB3_1 136 I/O (b) + ldd 3 FB3_2 135 I/O O XLXN_1049 2 FB3_3 134 I/O (b) Qa<9> 2 FB3_4 (b) (b) + lde 3 FB3_5 133 I/O O Qa<8> 2 FB3_6 (b) (b) + XLXI_32/Q<7> 2 FB3_7 (b) (b) + XLXI_32/Q<6> 2 FB3_8 (b) (b) + XLXI_32/Q<5> 2 FB3_9 (b) (b) + XLXI_32/Q<4> 2 FB3_10 (b) (b) + XLXI_32/Q<3> 2 FB3_11 (b) (b) + XLXI_32/Q<2> 2 FB3_12 (b) (b) + XLXI_32/Q<1> 2 FB3_13 (b) (b) + XLXN_1048 1 FB3_14 132 I/O (b) XLXI_32/Q<0> 1 FB3_15 (b) (b) + ldf 3 FB3_16 131 I/O O Signals Used by Logic in Function Block 1: Qa<8> 8: XLXI_32/Q<6> 14: XLXN_244 2: XLXI_32/Q<0> 9: XLXI_32/Q<7> 15: hex<0> 3: XLXI_32/Q<1> 10: XLXN_1041 16: hex<1> 4: XLXI_32/Q<2> 11: XLXN_1048 17: hex<2> 5: XLXI_32/Q<3> 12: XLXN_1061 18: hex<3> 6: XLXI_32/Q<4> 13: XLXN_1068 19: midiin 7: XLXI_32/Q<5> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs XLXN_1041 ...........XX.....X..................... 3 ldd ..............XXXX...................... 4 XLXN_1049 .........XX............................. 2 Qa<9> XXXXXXXXX....X.......................... 10 lde ..............XXXX...................... 4 Qa<8> .XXXXXXXX....X.......................... 9 XLXI_32/Q<7> .XXXXXXX.....X.......................... 8 XLXI_32/Q<6> .XXXXXX......X.......................... 7 XLXI_32/Q<5> .XXXXX.......X.......................... 6 XLXI_32/Q<4> .XXXX........X.......................... 5 XLXI_32/Q<3> .XXX.........X.......................... 4 XLXI_32/Q<2> .XX..........X.......................... 3 XLXI_32/Q<1> .X...........X.......................... 2 XLXN_1048 .........X.............................. 1 XLXI_32/Q<0> .............X.......................... 1 ldf ..............XXXX...................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 19/21 Number of function block control terms used/remaining: 1/3 Number of PLA product terms used/remaining: 23/33 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use db3 2 FB4_1 11 I/O O db2 2 FB4_2 12 I/O O db1 2 FB4_3 13 I/O O db0 2 FB4_4 14 I/O O e 2 FB4_5 15 I/O O rs 2 FB4_6 16 I/O O (unused) 0 FB4_7 (b) (unused) 0 FB4_8 (b) XLXN_1029 3 FB4_9 (b) (b) + XLXN_1028 3 FB4_10 (b) (b) + XLXN_1027 3 FB4_11 (b) (b) + (unused) 0 FB4_12 17 I/O I XLXN_1022 3 FB4_13 (b) (b) + (unused) 0 FB4_14 18 I/O I XLXN_1021 3 FB4_15 (b) (b) + XLXN_1020 3 FB4_16 (b) (b) + Signals Used by Logic in Function Block 1: A1 8: XLXN_1018 14: XLXN_1076 2: NAMS3 9: XLXN_1020 15: XLXN_929 3: NAWE 10: XLXN_1021 16: datab0.PIN 4: XLXI_277/Q0 11: XLXN_1022 17: datab1.PIN 5: XLXI_277/Q1 12: XLXN_1028 18: datab2.PIN 6: XLXI_277/Q2 13: XLXN_1072 19: datab3.PIN 7: XLXI_277/Q3 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs db3 XXX...............X..................... 4 db2 XXX..............X...................... 4 db1 XXX.............X....................... 4 db0 XXX............X........................ 4 e XXX.............X....................... 4 rs XXX............X........................ 4 XLXN_1029 ...XXXX.....XXX......................... 7 XLXN_1028 ...XXXXX....XX.......................... 7 XLXN_1027 ...XXXX...X.XX.......................... 7 XLXN_1022 ...XXXX..X..XX.......................... 7 XLXN_1021 ...XXXX.X...XX.......................... 7 XLXN_1020 ...XXXX....XXX.......................... 7 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB5_1 (b) (unused) 0 FB5_2 33 I/O (unused) 0 FB5_3 (b) (unused) 0 FB5_4 32 GCK/I/O (unused) 0 FB5_5 31 I/O (unused) 0 FB5_6 30 GCK/I/O (unused) 0 FB5_7 (b) (unused) 0 FB5_8 (b) (unused) 0 FB5_9 (b) (unused) 0 FB5_10 (b) (unused) 0 FB5_11 (b) (unused) 0 FB5_12 (b) (unused) 0 FB5_13 (b) (unused) 0 FB5_14 28 I/O (unused) 0 FB5_15 (b) (unused) 0 FB5_16 (b) *********************************** FB6 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB6_1 34 I/O (unused) 0 FB6_2 35 CDR/I/O (unused) 0 FB6_3 (b) (unused) 0 FB6_4 38 GCK/I/O GCK (unused) 0 FB6_5 (b) (unused) 0 FB6_6 (b) (unused) 0 FB6_7 (b) (unused) 0 FB6_8 (b) (unused) 0 FB6_9 (b) (unused) 0 FB6_10 (b) (unused) 0 FB6_11 (b) (unused) 0 FB6_12 39 DGE/I/O (unused) 0 FB6_13 40 I/O (unused) 0 FB6_14 41 I/O (unused) 0 FB6_15 42 I/O (unused) 0 FB6_16 43 I/O *********************************** FB7 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB7_1 (b) (unused) 0 FB7_2 (b) (unused) 0 FB7_3 (b) (unused) 0 FB7_4 (b) (unused) 0 FB7_5 26 I/O (unused) 0 FB7_6 25 I/O (unused) 0 FB7_7 (b) (unused) 0 FB7_8 (b) (unused) 0 FB7_9 (b) (unused) 0 FB7_10 (b) (unused) 0 FB7_11 24 I/O (unused) 0 FB7_12 23 I/O (unused) 0 FB7_13 22 I/O (unused) 0 FB7_14 21 I/O (unused) 0 FB7_15 20 I/O (unused) 0 FB7_16 19 I/O *********************************** FB8 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB8_1 44 I/O (unused) 0 FB8_2 45 I/O (unused) 0 FB8_3 46 I/O (unused) 0 FB8_4 (b) (unused) 0 FB8_5 48 I/O (unused) 0 FB8_6 49 I/O (unused) 0 FB8_7 (b) (unused) 0 FB8_8 (b) (unused) 0 FB8_9 (b) (unused) 0 FB8_10 (b) (unused) 0 FB8_11 50 I/O (unused) 0 FB8_12 51 I/O (unused) 0 FB8_13 52 I/O (unused) 0 FB8_14 (b) (unused) 0 FB8_15 (b) (unused) 0 FB8_16 (b) *********************************** FB9 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 19/21 Number of function block control terms used/remaining: 1/3 Number of PLA product terms used/remaining: 16/40 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB9_1 112 I/O I (unused) 0 FB9_2 113 I/O I (unused) 0 FB9_3 (b) (unused) 0 FB9_4 114 I/O I (unused) 0 FB9_5 (b) datab0 4 FB9_6 115 I/O I/O + (unused) 0 FB9_7 (b) (unused) 0 FB9_8 (b) (unused) 0 FB9_9 (b) (unused) 0 FB9_10 (b) (unused) 0 FB9_11 (b) datab2 4 FB9_12 116 I/O I/O + datab4 4 FB9_13 117 I/O I/O + datab6 4 FB9_14 118 I/O I/O + datab7 4 FB9_15 119 I/O I/O + (unused) 0 FB9_16 (b) Signals Used by Logic in Function Block 1: A1 8: XLXN_1028 14: hex<0> 2: A2 9: XLXN_1029 15: hex<2> 3: NAMS3 10: XLXN_1048 16: ll1 4: NARE 11: XLXN_1049 17: ll3 5: Qa<8> 12: XLXN_929 18: ll5 6: XLXN_1021 13: butr 19: qold 7: XLXN_1027 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs datab0 XXXX..X......X.X........................ 7 datab2 XXXX.X........X.X....................... 7 datab4 XXXXX..X.........X...................... 7 datab6 XXXX....XX..X........................... 7 datab7 XXXX......XX......X..................... 7 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB10 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB10_1 111 I/O I (unused) 0 FB10_2 110 I/O I (unused) 0 FB10_3 107 I/O (unused) 0 FB10_4 106 I/O (unused) 0 FB10_5 105 I/O (unused) 0 FB10_6 104 I/O (unused) 0 FB10_7 (b) (unused) 0 FB10_8 (b) (unused) 0 FB10_9 (b) (unused) 0 FB10_10 (b) (unused) 0 FB10_11 (b) (unused) 0 FB10_12 103 I/O (unused) 0 FB10_13 (b) (unused) 0 FB10_14 102 I/O (unused) 0 FB10_15 (b) (unused) 0 FB10_16 101 I/O *********************************** FB11 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 21/19 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 15/41 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB11_1 (b) (unused) 0 FB11_2 (b) (unused) 0 FB11_3 (b) (unused) 0 FB11_4 (b) datab5 4 FB11_5 120 I/O I/O + datab3 4 FB11_6 121 I/O I/O + (unused) 0 FB11_7 (b) (unused) 0 FB11_8 (b) (unused) 0 FB11_9 (b) (unused) 0 FB11_10 (b) datab1 4 FB11_11 124 I/O I/O + (unused) 0 FB11_12 125 I/O (unused) 0 FB11_13 126 I/O XLXN_929 2 FB11_14 128 I/O I + ldg 3 FB11_15 129 I/O O (unused) 0 FB11_16 130 I/O Signals Used by Logic in Function Block 1: A1 8: XLXI_277/Q3 15: butl 2: A2 9: XLXN_1018 16: hex<0> 3: NAMS3 10: XLXN_1020 17: hex<1> 4: NARE 11: XLXN_1022 18: hex<2> 5: XLXI_277/Q0 12: XLXN_1041 19: hex<3> 6: XLXI_277/Q1 13: XLXN_1072 20: ll2 7: XLXI_277/Q2 14: XLXN_1076 21: ll4 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs datab5 XXXX....X..X..X......................... 7 datab3 XXXX.....X........X.X................... 7 datab1 XXXX......X.....X..X.................... 7 ldg ...............XXXX..................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB12 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB12_1 (b) (unused) 0 FB12_2 100 I/O (unused) 0 FB12_3 (b) (unused) 0 FB12_4 (b) (unused) 0 FB12_5 (b) (unused) 0 FB12_6 (b) (unused) 0 FB12_7 (b) (unused) 0 FB12_8 (b) (unused) 0 FB12_9 (b) (unused) 0 FB12_10 (b) (unused) 0 FB12_11 98 I/O (unused) 0 FB12_12 97 I/O (unused) 0 FB12_13 96 I/O (unused) 0 FB12_14 95 I/O (unused) 0 FB12_15 94 I/O (unused) 0 FB12_16 (b) *********************************** FB13 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 2/38 Number of function block control terms used/remaining: 1/3 Number of PLA product terms used/remaining: 2/54 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB13_1 75 I/O (unused) 0 FB13_2 76 I/O (unused) 0 FB13_3 77 I/O (unused) 0 FB13_4 (b) (unused) 0 FB13_5 78 I/O I ll5 1 FB13_6 79 I/O O (unused) 0 FB13_7 (b) (unused) 0 FB13_8 (b) (unused) 0 FB13_9 (b) (unused) 0 FB13_10 (b) (unused) 0 FB13_11 (b) (unused) 0 FB13_12 80 I/O I ll4 1 FB13_13 81 I/O O + (unused) 0 FB13_14 82 I/O I (unused) 0 FB13_15 (b) (unused) 0 FB13_16 (b) Signals Used by Logic in Function Block 1: bl4 2: bl5 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ll5 .X...................................... 1 ll4 X....................................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB14 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB14_1 74 I/O (unused) 0 FB14_2 71 I/O (unused) 0 FB14_3 70 I/O (unused) 0 FB14_4 69 I/O (unused) 0 FB14_5 (b) (unused) 0 FB14_6 68 I/O (unused) 0 FB14_7 (b) (unused) 0 FB14_8 (b) (unused) 0 FB14_9 (b) (unused) 0 FB14_10 (b) (unused) 0 FB14_11 (b) (unused) 0 FB14_12 (b) (unused) 0 FB14_13 66 I/O (unused) 0 FB14_14 64 I/O (unused) 0 FB14_15 (b) (unused) 0 FB14_16 61 I/O *********************************** FB15 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 7/33 Number of function block control terms used/remaining: 1/3 Number of PLA product terms used/remaining: 5/51 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB15_1 (b) ll3 1 FB15_2 83 I/O O (unused) 0 FB15_3 (b) (unused) 0 FB15_4 (b) (unused) 0 FB15_5 (b) (unused) 0 FB15_6 (b) (unused) 0 FB15_7 (b) (unused) 0 FB15_8 (b) (unused) 0 FB15_9 (b) (unused) 0 FB15_10 (b) (unused) 0 FB15_11 85 I/O I ll2 1 FB15_12 86 I/O O (unused) 0 FB15_13 87 I/O I ll1 1 FB15_14 88 I/O O (unused) 0 FB15_15 91 I/O boardled1 2 FB15_16 92 I/O O + Signals Used by Logic in Function Block 1: A1 4: bl1 6: bl3 2: NAMS3 5: bl2 7: datab0.PIN 3: NAWE Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ll3 .....X.................................. 1 ll2 ....X................................... 1 ll1 ...X.................................... 1 boardled1 XXX...X................................. 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB16 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB16_1 (b) (unused) 0 FB16_2 (b) (unused) 0 FB16_3 (b) (unused) 0 FB16_4 (b) (unused) 0 FB16_5 60 I/O (unused) 0 FB16_6 59 I/O (unused) 0 FB16_7 (b) (unused) 0 FB16_8 (b) (unused) 0 FB16_9 (b) (unused) 0 FB16_10 (b) (unused) 0 FB16_11 58 I/O (unused) 0 FB16_12 57 I/O (unused) 0 FB16_13 56 I/O (unused) 0 FB16_14 (b) (unused) 0 FB16_15 54 I/O (unused) 0 FB16_16 53 I/O ******************************* Equations ******************************** ********** Mapped Logic ********** N_PZ_340 <= ((XLXN_268 AND NOT Qa(9) AND NOT XLXN_287 AND XLXN_280 AND XLXN_281) OR (XLXN_268 AND NOT Qa(9) AND NOT XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281) OR (NOT XLXN_268 AND NOT Qa(9) AND XLXN_287 AND XLXN_280 AND XLXN_281) OR (NOT XLXN_268 AND NOT Qa(9) AND XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281)); FTCPE_Qa8: FTCPE port map (Qa(8),Qa_T(8),XLXN_244,'0','0','1'); Qa_T(8) <= (XLXI_32/Q(0) AND XLXI_32/Q(4) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3) AND XLXI_32/Q(5) AND XLXI_32/Q(6) AND XLXI_32/Q(7)); FTCPE_Qa9: FTCPE port map (Qa(9),Qa_T(9),XLXN_244,'0','0','1'); Qa_T(9) <= (XLXI_32/Q(0) AND XLXI_32/Q(4) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3) AND XLXI_32/Q(5) AND Qa(8) AND XLXI_32/Q(6) AND XLXI_32/Q(7)); FTCPE_XLXI_277/Q0: FTCPE port map (XLXI_277/Q0,XLXI_277/Q0_T,clock_in,XLXN_1041,'0','1'); XLXI_277/Q0_T <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); FTCPE_XLXI_277/Q1: FTCPE port map (XLXI_277/Q1,XLXI_277/Q0,clock_in,XLXN_1041,'0','1'); FTCPE_XLXI_277/Q2: FTCPE port map (XLXI_277/Q2,XLXI_277/Q2_T,clock_in,XLXN_1041,'0','1'); XLXI_277/Q2_T <= (XLXI_277/Q0 AND XLXI_277/Q1); FTCPE_XLXI_277/Q3: FTCPE port map (XLXI_277/Q3,XLXI_277/Q3_T,clock_in,XLXN_1041,'0','1'); XLXI_277/Q3_T <= (XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2); FTCPE_XLXI_287/Q1: FTCPE port map (XLXI_287/Q1,XLXI_287/Q1_T,XLXI_287/Q1_C,XLXN_1041,'0','1'); XLXI_287/Q1_T <= (XLXN_1072 AND XLXN_1068 AND NOT XLXN_1076); XLXI_287/Q1_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); FTCPE_XLXI_287/Q2: FTCPE port map (XLXI_287/Q2,XLXI_287/Q2_T,XLXI_287/Q2_C,XLXN_1041,'0','1'); XLXI_287/Q2_T <= (XLXN_1072 AND XLXN_1068 AND NOT XLXN_1076 AND XLXI_287/Q1); XLXI_287/Q2_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); FTCPE_XLXI_32/Q0: FTCPE port map (XLXI_32/Q(0),'0',XLXN_244,'0','0','1'); FTCPE_XLXI_32/Q1: FTCPE port map (XLXI_32/Q(1),XLXI_32/Q(0),XLXN_244,'0','0','1'); FTCPE_XLXI_32/Q2: FTCPE port map (XLXI_32/Q(2),XLXI_32/Q_T(2),XLXN_244,'0','0','1'); XLXI_32/Q_T(2) <= (XLXI_32/Q(0) AND XLXI_32/Q(1)); FTCPE_XLXI_32/Q3: FTCPE port map (XLXI_32/Q(3),XLXI_32/Q_T(3),XLXN_244,'0','0','1'); XLXI_32/Q_T(3) <= (XLXI_32/Q(0) AND XLXI_32/Q(1) AND XLXI_32/Q(2)); FTCPE_XLXI_32/Q4: FTCPE port map (XLXI_32/Q(4),XLXI_32/Q_T(4),XLXN_244,'0','0','1'); XLXI_32/Q_T(4) <= (XLXI_32/Q(0) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3)); FTCPE_XLXI_32/Q5: FTCPE port map (XLXI_32/Q(5),XLXI_32/Q_T(5),XLXN_244,'0','0','1'); XLXI_32/Q_T(5) <= (XLXI_32/Q(0) AND XLXI_32/Q(4) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3)); FTCPE_XLXI_32/Q6: FTCPE port map (XLXI_32/Q(6),XLXI_32/Q_T(6),XLXN_244,'0','0','1'); XLXI_32/Q_T(6) <= (XLXI_32/Q(0) AND XLXI_32/Q(4) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3) AND XLXI_32/Q(5)); FTCPE_XLXI_32/Q7: FTCPE port map (XLXI_32/Q(7),XLXI_32/Q_T(7),XLXN_244,'0','0','1'); XLXI_32/Q_T(7) <= (XLXI_32/Q(0) AND XLXI_32/Q(4) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3) AND XLXI_32/Q(5) AND XLXI_32/Q(6)); FTCPE_XLXI_36/Q0: FTCPE port map (XLXI_36/Q0,'0',clock_in,'0','0','1'); FTCPE_XLXI_36/Q1: FTCPE port map (XLXI_36/Q1,XLXI_36/Q0,clock_in,'0','0','1'); FTCPE_XLXI_36/Q2: FTCPE port map (XLXI_36/Q2,XLXI_36/Q2_T,clock_in,'0','0','1'); XLXI_36/Q2_T <= (XLXI_36/Q0 AND XLXI_36/Q1); FDCPE_XLXN_1018: FDCPE port map (XLXN_1018,XLXN_1029,XLXN_1018_C,'0','0',XLXN_1018_CE); XLXN_1018_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1018_CE <= (XLXN_1072 AND NOT XLXN_1076); FDCPE_XLXN_1020: FDCPE port map (XLXN_1020,XLXN_1028,XLXN_1020_C,'0','0',XLXN_1020_CE); XLXN_1020_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1020_CE <= (XLXN_1072 AND NOT XLXN_1076); FDCPE_XLXN_1021: FDCPE port map (XLXN_1021,XLXN_1020,XLXN_1021_C,'0','0',XLXN_1021_CE); XLXN_1021_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1021_CE <= (XLXN_1072 AND NOT XLXN_1076); FDCPE_XLXN_1022: FDCPE port map (XLXN_1022,XLXN_1021,XLXN_1022_C,'0','0',XLXN_1022_CE); XLXN_1022_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1022_CE <= (XLXN_1072 AND NOT XLXN_1076); FDCPE_XLXN_1027: FDCPE port map (XLXN_1027,XLXN_1022,XLXN_1027_C,'0','0',XLXN_1027_CE); XLXN_1027_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1027_CE <= (XLXN_1072 AND NOT XLXN_1076); FDCPE_XLXN_1028: FDCPE port map (XLXN_1028,XLXN_1018,XLXN_1028_C,'0','0',XLXN_1028_CE); XLXN_1028_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1028_CE <= (XLXN_1072 AND NOT XLXN_1076); FDCPE_XLXN_1029: FDCPE port map (XLXN_1029,XLXN_929,XLXN_1029_C,'0','0',XLXN_1029_CE); XLXN_1029_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1029_CE <= (XLXN_1072 AND NOT XLXN_1076); FDCPE_XLXN_1041: FDCPE port map (XLXN_1041,'0',midiin,'0',XLXN_1041_PRE,'1'); XLXN_1041_PRE <= (XLXN_1068 AND XLXN_1061); FTCPE_XLXN_1048: FTCPE port map (XLXN_1048,'0',XLXN_1041,'0','0','1'); FTCPE_XLXN_1049: FTCPE port map (XLXN_1049,XLXN_1048,XLXN_1041,'0','0','1'); FTCPE_XLXN_1061: FTCPE port map (XLXN_1061,XLXN_1061_T,XLXN_1061_C,XLXN_1041,'0','1'); XLXN_1061_T <= (XLXN_1072 AND XLXN_1068 AND NOT XLXN_1076 AND XLXI_287/Q1 AND XLXI_287/Q2); XLXN_1061_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); FTCPE_XLXN_1068: FTCPE port map (XLXN_1068,XLXN_1068_T,XLXN_1068_C,XLXN_1041,'0','1'); XLXN_1068_T <= (XLXN_1072 AND NOT XLXN_1076); XLXN_1068_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); FTCPE_XLXN_1072: FTCPE port map (XLXN_1072,'0',XLXN_1072_C,XLXN_1041,'0','1'); XLXN_1072_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); FTCPE_XLXN_1076: FTCPE port map (XLXN_1076,XLXN_1072,XLXN_1076_C,XLXN_1041,'0','1'); XLXN_1076_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); FTCPE_XLXN_244: FTCPE port map (XLXN_244,XLXN_244_T,clock_in,'0','0','1'); XLXN_244_T <= (XLXI_36/Q0 AND XLXI_36/Q1 AND XLXI_36/Q2); XLXN_268.COMB <= (qold AND b);FDCPE_XLXN_268: FDCPE port map (XLXN_268,rotl,Qa(9),'0','0','1'); FDCPE_XLXN_280: FDCPE port map (XLXN_280,XLXN_268,Qa(9),'0','0','1'); FDCPE_XLXN_281: FDCPE port map (XLXN_281,XLXN_287,Qa(9),'0','0','1'); FDCPE_XLXN_287: FDCPE port map (XLXN_287,rotr,Qa(9),'0','0','1'); FDCPE_XLXN_929: FDCPE port map (XLXN_929,midiin,XLXN_929_C,'0','0',XLXN_929_CE); XLXN_929_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_929_CE <= (XLXN_1072 AND NOT XLXN_1076); FDCPE_boardled1: FDCPE port map (boardled1,NOT datab0.PIN,boardled1_C,'0','0','1'); boardled1_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); datab0_I <= NOT (((NOT A1 AND NOT hex(0)) OR (A1 AND A2 AND ll1) OR (A1 AND NOT A2 AND NOT XLXN_1027))); datab0 <= datab0_I when datab0_OE = '1' else 'Z'; datab0_OE <= (NOT NAMS3 AND NOT NARE); datab1_I <= NOT (((NOT A1 AND NOT hex(1)) OR (A1 AND A2 AND ll2) OR (A1 AND NOT A2 AND NOT XLXN_1022))); datab1 <= datab1_I when datab1_OE = '1' else 'Z'; datab1_OE <= (NOT NAMS3 AND NOT NARE); datab2_I <= NOT (((NOT A1 AND NOT hex(2)) OR (A1 AND A2 AND ll3) OR (A1 AND NOT A2 AND NOT XLXN_1021))); datab2 <= datab2_I when datab2_OE = '1' else 'Z'; datab2_OE <= (NOT NAMS3 AND NOT NARE); datab3_I <= NOT (((NOT A1 AND NOT hex(3)) OR (A1 AND A2 AND ll4) OR (A1 AND NOT A2 AND NOT XLXN_1020))); datab3 <= datab3_I when datab3_OE = '1' else 'Z'; datab3_OE <= (NOT NAMS3 AND NOT NARE); datab4_I <= NOT (((NOT A1 AND NOT Qa(8)) OR (A1 AND A2 AND ll5) OR (A1 AND NOT A2 AND NOT XLXN_1028))); datab4 <= datab4_I when datab4_OE = '1' else 'Z'; datab4_OE <= (NOT NAMS3 AND NOT NARE); datab5_I <= NOT (((NOT A1 AND NOT butl) OR (A1 AND A2 AND NOT XLXN_1041) OR (A1 AND NOT A2 AND NOT XLXN_1018))); datab5 <= datab5_I when datab5_OE = '1' else 'Z'; datab5_OE <= (NOT NAMS3 AND NOT NARE); datab6_I <= NOT (((NOT A1 AND NOT butr) OR (A1 AND A2 AND NOT XLXN_1048) OR (A1 AND NOT A2 AND NOT XLXN_1029))); datab6 <= datab6_I when datab6_OE = '1' else 'Z'; datab6_OE <= (NOT NAMS3 AND NOT NARE); datab7_I <= NOT (((NOT A1 AND NOT qold) OR (A1 AND A2 AND NOT XLXN_1049) OR (A1 AND NOT A2 AND NOT XLXN_929))); datab7 <= datab7_I when datab7_OE = '1' else 'Z'; datab7_OE <= (NOT NAMS3 AND NOT NARE); FDCPE_db0: FDCPE port map (db0,datab0.PIN,db0_C,'0','0','1'); db0_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); FDCPE_db1: FDCPE port map (db1,datab1.PIN,db1_C,'0','0','1'); db1_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); FDCPE_db2: FDCPE port map (db2,datab2.PIN,db2_C,'0','0','1'); db2_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); FDCPE_db3: FDCPE port map (db3,datab3.PIN,db3_C,'0','0','1'); db3_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); FDCPE_db4: FDCPE port map (db4,datab4.PIN,db4_C,'0','0','1'); db4_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); FDCPE_db5: FDCPE port map (db5,datab5.PIN,db5_C,'0','0','1'); db5_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); FDCPE_db6: FDCPE port map (db6,datab6.PIN,db6_C,'0','0','1'); db6_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); FDCPE_db7: FDCPE port map (db7,datab7.PIN,db7_C,'0','0','1'); db7_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); FDCPE_e: FDCPE port map (e,datab1.PIN,e_C,'0','0','1'); e_C <= NOT ((NOT NAWE AND NOT NAMS3 AND A1)); FTCPE_hex0: FTCPE port map (hex(0),'0',N_PZ_340,NOT XLXN_268.COMB,'0','1'); FTCPE_hex1: FTCPE port map (hex(1),hex_T(1),N_PZ_340,NOT XLXN_268.COMB,'0','1'); hex_T(1) <= NOT (hex(0) XOR ((XLXN_268 AND NOT XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281) OR (NOT XLXN_268 AND XLXN_287 AND XLXN_280 AND XLXN_281))); FTCPE_hex2: FTCPE port map (hex(2),hex_T(2),N_PZ_340,NOT XLXN_268.COMB,'0','1'); hex_T(2) <= NOT ((hex(0) AND hex(1)) XOR ((hex(0) AND NOT hex(1)) OR (NOT hex(0) AND hex(1)) OR (XLXN_268 AND NOT XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281) OR (NOT XLXN_268 AND XLXN_287 AND XLXN_280 AND XLXN_281))); FTCPE_hex3: FTCPE port map (hex(3),hex_T(3),N_PZ_340,NOT XLXN_268.COMB,'0','1'); hex_T(3) <= (NOT hex(0) AND NOT hex(1) AND NOT hex(2)) XOR ((hex(0) AND XLXN_268 AND NOT XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281 AND hex(1) AND hex(2)) OR (hex(0) AND NOT XLXN_268 AND XLXN_287 AND XLXN_280 AND XLXN_281 AND hex(1) AND hex(2)) OR (NOT hex(0) AND XLXN_268 AND NOT XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281 AND NOT hex(1) AND NOT hex(2)) OR (NOT hex(0) AND NOT XLXN_268 AND XLXN_287 AND XLXN_280 AND XLXN_281 AND NOT hex(1) AND NOT hex(2))); lda <= (NOT hex(0) AND hex(2)) XOR ((hex(0) AND hex(1) AND hex(3)) OR (NOT hex(1) AND hex(2) AND NOT hex(3))); ldb <= ((NOT hex(0) AND hex(2) AND hex(3)) OR (hex(1) AND hex(2) AND hex(3)) OR (NOT hex(0) AND hex(1) AND NOT hex(2) AND NOT hex(3))); ldc <= ((hex(0) AND hex(1) AND hex(2)) OR (hex(0) AND NOT hex(1) AND NOT hex(2)) OR (NOT hex(0) AND hex(1) AND NOT hex(2) AND hex(3)) OR (NOT hex(0) AND NOT hex(1) AND hex(2) AND NOT hex(3))); ldd <= ((hex(0) AND NOT hex(3)) OR (hex(0) AND NOT hex(1) AND NOT hex(2)) OR (NOT hex(1) AND hex(2) AND NOT hex(3))); lde <= (hex(0) AND NOT hex(3)) XOR ((hex(0) AND NOT hex(1) AND hex(2)) OR (NOT hex(0) AND hex(1) AND NOT hex(2) AND NOT hex(3))); ldf <= (hex(0) AND NOT hex(1)) XOR ((hex(0) AND NOT hex(2) AND hex(3)) OR (NOT hex(1) AND hex(2) AND NOT hex(3))); ldg <= ((NOT hex(1) AND NOT hex(2) AND NOT hex(3)) OR (hex(0) AND hex(1) AND hex(2) AND NOT hex(3)) OR (NOT hex(0) AND NOT hex(1) AND hex(2) AND hex(3))); FTCPE_ll1: FTCPE port map (ll1,'0',bl1,'0','0','1'); FTCPE_ll2: FTCPE port map (ll2,'0',bl2,'0','0','1'); FTCPE_ll3: FTCPE port map (ll3,'0',bl3,'0','0','1'); FTCPE_ll4: FTCPE port map (ll4,'0',bl4,'0','0','1'); FTCPE_ll5: FTCPE port map (ll5,'0',bl5,'0','0','1'); qold <= NOT ((NOT XLXN_268.COMB AND a)); FDCPE_rs: FDCPE port map (rs,datab0.PIN,rs_C,'0','0','1'); rs_C <= NOT ((NOT NAWE AND NOT NAMS3 AND A1)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC2C256-7-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCCIO-3.3 2 rotl 74 KPR 3 a 75 KPR 4 rotr 76 KPR 5 b 77 KPR 6 db7 78 bl5 7 db6 79 ll5 8 VCCAUX 80 bl4 9 db5 81 ll4 10 db4 82 bl3 11 db3 83 ll3 12 db2 84 VCC 13 db1 85 bl2 14 db0 86 ll2 15 e 87 bl1 16 rs 88 ll1 17 butr 89 GND 18 butl 90 GND 19 KPR 91 KPR 20 KPR 92 boardled1 21 KPR 93 VCCIO-3.3 22 KPR 94 KPR 23 KPR 95 KPR 24 KPR 96 KPR 25 KPR 97 KPR 26 KPR 98 KPR 27 VCCIO-3.3 99 GND 28 KPR 100 KPR 29 GND 101 KPR 30 KPR 102 KPR 31 KPR 103 KPR 32 KPR 104 KPR 33 KPR 105 KPR 34 KPR 106 KPR 35 KPR 107 KPR 36 GND 108 GND 37 VCC 109 VCCIO-3.3 38 clock_in 110 NARE 39 KPR 111 NAWE 40 KPR 112 NAMS3 41 KPR 113 A2 42 KPR 114 A1 43 KPR 115 datab0 44 KPR 116 datab2 45 KPR 117 datab4 46 KPR 118 datab6 47 GND 119 datab7 48 KPR 120 datab5 49 KPR 121 datab3 50 KPR 122 TDO 51 KPR 123 GND 52 KPR 124 datab1 53 KPR 125 KPR 54 KPR 126 KPR 55 VCCIO-3.3 127 VCCIO-3.3 56 KPR 128 midiin 57 KPR 129 ldg 58 KPR 130 KPR 59 KPR 131 ldf 60 KPR 132 KPR 61 KPR 133 lde 62 GND 134 KPR 63 TDI 135 ldd 64 KPR 136 KPR 65 TMS 137 ldc 66 KPR 138 KPR 67 TCK 139 ldb 68 KPR 140 KPR 69 KPR 141 VCCIO-3.3 70 KPR 142 lda 71 KPR 143 KPR 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin KPR = Unused I/O with weak keeper (leave unconnected) WPU = Unused I/O with weak pull up (leave unconnected) TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin VCCAUX = Power supply for JTAG pins VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I VCCIO-1.8 = I/O supply voltage for LVCMOS18 VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I VREF = Reference voltage for indicated input standard *VREF = Reference voltage pin selected by software GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc2c256-7-TQ144 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Set Unused I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Enable Input Registers : ON Function Block Fan-in Limit : 38 Use DATA_GATE Attribute : ON Set Tristate Outputs to Termination Mode : KEEPER Default Voltage Standard for All Outputs : LVCMOS18 Input Limit : 32 Pterm Limit : 28