********** Mapped Logic ********** |
N_PZ_340 <= ((XLXN_268 AND NOT Qa(9) AND NOT XLXN_287 AND XLXN_280 AND
XLXN_281) OR (XLXN_268 AND NOT Qa(9) AND NOT XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281) OR (NOT XLXN_268 AND NOT Qa(9) AND XLXN_287 AND XLXN_280 AND XLXN_281) OR (NOT XLXN_268 AND NOT Qa(9) AND XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281)); |
FTCPE_Qa8: FTCPE port map (Qa(8),Qa_T(8),XLXN_244,'0','0','1');
Qa_T(8) <= (XLXI_32/Q(0) AND XLXI_32/Q(4) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3) AND XLXI_32/Q(5) AND XLXI_32/Q(6) AND XLXI_32/Q(7)); |
FTCPE_Qa9: FTCPE port map (Qa(9),Qa_T(9),XLXN_244,'0','0','1');
Qa_T(9) <= (XLXI_32/Q(0) AND XLXI_32/Q(4) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3) AND XLXI_32/Q(5) AND Qa(8) AND XLXI_32/Q(6) AND XLXI_32/Q(7)); |
FTCPE_XLXI_277/Q0: FTCPE port map (XLXI_277/Q0,XLXI_277/Q0_T,clock_in,XLXN_1041,'0','1');
XLXI_277/Q0_T <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); |
FTCPE_XLXI_277/Q1: FTCPE port map (XLXI_277/Q1,XLXI_277/Q0,clock_in,XLXN_1041,'0','1'); |
FTCPE_XLXI_277/Q2: FTCPE port map (XLXI_277/Q2,XLXI_277/Q2_T,clock_in,XLXN_1041,'0','1');
XLXI_277/Q2_T <= (XLXI_277/Q0 AND XLXI_277/Q1); |
FTCPE_XLXI_277/Q3: FTCPE port map (XLXI_277/Q3,XLXI_277/Q3_T,clock_in,XLXN_1041,'0','1');
XLXI_277/Q3_T <= (XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2); |
FTCPE_XLXI_287/Q1: FTCPE port map (XLXI_287/Q1,XLXI_287/Q1_T,XLXI_287/Q1_C,XLXN_1041,'0','1');
XLXI_287/Q1_T <= (XLXN_1072 AND XLXN_1068 AND NOT XLXN_1076); XLXI_287/Q1_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); |
FTCPE_XLXI_287/Q2: FTCPE port map (XLXI_287/Q2,XLXI_287/Q2_T,XLXI_287/Q2_C,XLXN_1041,'0','1');
XLXI_287/Q2_T <= (XLXN_1072 AND XLXN_1068 AND NOT XLXN_1076 AND XLXI_287/Q1); XLXI_287/Q2_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); |
FTCPE_XLXI_32/Q0: FTCPE port map (XLXI_32/Q(0),'0',XLXN_244,'0','0','1'); |
FTCPE_XLXI_32/Q1: FTCPE port map (XLXI_32/Q(1),XLXI_32/Q(0),XLXN_244,'0','0','1'); |
FTCPE_XLXI_32/Q2: FTCPE port map (XLXI_32/Q(2),XLXI_32/Q_T(2),XLXN_244,'0','0','1');
XLXI_32/Q_T(2) <= (XLXI_32/Q(0) AND XLXI_32/Q(1)); |
FTCPE_XLXI_32/Q3: FTCPE port map (XLXI_32/Q(3),XLXI_32/Q_T(3),XLXN_244,'0','0','1');
XLXI_32/Q_T(3) <= (XLXI_32/Q(0) AND XLXI_32/Q(1) AND XLXI_32/Q(2)); |
FTCPE_XLXI_32/Q4: FTCPE port map (XLXI_32/Q(4),XLXI_32/Q_T(4),XLXN_244,'0','0','1');
XLXI_32/Q_T(4) <= (XLXI_32/Q(0) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3)); |
FTCPE_XLXI_32/Q5: FTCPE port map (XLXI_32/Q(5),XLXI_32/Q_T(5),XLXN_244,'0','0','1');
XLXI_32/Q_T(5) <= (XLXI_32/Q(0) AND XLXI_32/Q(4) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3)); |
FTCPE_XLXI_32/Q6: FTCPE port map (XLXI_32/Q(6),XLXI_32/Q_T(6),XLXN_244,'0','0','1');
XLXI_32/Q_T(6) <= (XLXI_32/Q(0) AND XLXI_32/Q(4) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3) AND XLXI_32/Q(5)); |
FTCPE_XLXI_32/Q7: FTCPE port map (XLXI_32/Q(7),XLXI_32/Q_T(7),XLXN_244,'0','0','1');
XLXI_32/Q_T(7) <= (XLXI_32/Q(0) AND XLXI_32/Q(4) AND XLXI_32/Q(1) AND XLXI_32/Q(2) AND XLXI_32/Q(3) AND XLXI_32/Q(5) AND XLXI_32/Q(6)); |
FTCPE_XLXI_36/Q0: FTCPE port map (XLXI_36/Q0,'0',clock_in,'0','0','1'); |
FTCPE_XLXI_36/Q1: FTCPE port map (XLXI_36/Q1,XLXI_36/Q0,clock_in,'0','0','1'); |
FTCPE_XLXI_36/Q2: FTCPE port map (XLXI_36/Q2,XLXI_36/Q2_T,clock_in,'0','0','1');
XLXI_36/Q2_T <= (XLXI_36/Q0 AND XLXI_36/Q1); |
FDCPE_XLXN_1018: FDCPE port map (XLXN_1018,XLXN_1029,XLXN_1018_C,'0','0',XLXN_1018_CE);
XLXN_1018_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1018_CE <= (XLXN_1072 AND NOT XLXN_1076); |
FDCPE_XLXN_1020: FDCPE port map (XLXN_1020,XLXN_1028,XLXN_1020_C,'0','0',XLXN_1020_CE);
XLXN_1020_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1020_CE <= (XLXN_1072 AND NOT XLXN_1076); |
FDCPE_XLXN_1021: FDCPE port map (XLXN_1021,XLXN_1020,XLXN_1021_C,'0','0',XLXN_1021_CE);
XLXN_1021_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1021_CE <= (XLXN_1072 AND NOT XLXN_1076); |
FDCPE_XLXN_1022: FDCPE port map (XLXN_1022,XLXN_1021,XLXN_1022_C,'0','0',XLXN_1022_CE);
XLXN_1022_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1022_CE <= (XLXN_1072 AND NOT XLXN_1076); |
FDCPE_XLXN_1027: FDCPE port map (XLXN_1027,XLXN_1022,XLXN_1027_C,'0','0',XLXN_1027_CE);
XLXN_1027_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1027_CE <= (XLXN_1072 AND NOT XLXN_1076); |
FDCPE_XLXN_1028: FDCPE port map (XLXN_1028,XLXN_1018,XLXN_1028_C,'0','0',XLXN_1028_CE);
XLXN_1028_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1028_CE <= (XLXN_1072 AND NOT XLXN_1076); |
FDCPE_XLXN_1029: FDCPE port map (XLXN_1029,XLXN_929,XLXN_1029_C,'0','0',XLXN_1029_CE);
XLXN_1029_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_1029_CE <= (XLXN_1072 AND NOT XLXN_1076); |
FDCPE_XLXN_1041: FDCPE port map (XLXN_1041,'0',midiin,'0',XLXN_1041_PRE,'1');
XLXN_1041_PRE <= (XLXN_1068 AND XLXN_1061); |
FTCPE_XLXN_1048: FTCPE port map (XLXN_1048,'0',XLXN_1041,'0','0','1'); |
FTCPE_XLXN_1049: FTCPE port map (XLXN_1049,XLXN_1048,XLXN_1041,'0','0','1'); |
FTCPE_XLXN_1061: FTCPE port map (XLXN_1061,XLXN_1061_T,XLXN_1061_C,XLXN_1041,'0','1');
XLXN_1061_T <= (XLXN_1072 AND XLXN_1068 AND NOT XLXN_1076 AND XLXI_287/Q1 AND XLXI_287/Q2); XLXN_1061_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); |
FTCPE_XLXN_1068: FTCPE port map (XLXN_1068,XLXN_1068_T,XLXN_1068_C,XLXN_1041,'0','1');
XLXN_1068_T <= (XLXN_1072 AND NOT XLXN_1076); XLXN_1068_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); |
FTCPE_XLXN_1072: FTCPE port map (XLXN_1072,'0',XLXN_1072_C,XLXN_1041,'0','1');
XLXN_1072_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); |
FTCPE_XLXN_1076: FTCPE port map (XLXN_1076,XLXN_1072,XLXN_1076_C,XLXN_1041,'0','1');
XLXN_1076_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); |
FTCPE_XLXN_244: FTCPE port map (XLXN_244,XLXN_244_T,clock_in,'0','0','1');
XLXN_244_T <= (XLXI_36/Q0 AND XLXI_36/Q1 AND XLXI_36/Q2); |
XLXN_268.COMB <= (qold AND b);FDCPE_XLXN_268: FDCPE port map (XLXN_268,rotl,Qa(9),'0','0','1'); |
FDCPE_XLXN_280: FDCPE port map (XLXN_280,XLXN_268,Qa(9),'0','0','1'); |
FDCPE_XLXN_281: FDCPE port map (XLXN_281,XLXN_287,Qa(9),'0','0','1'); |
FDCPE_XLXN_287: FDCPE port map (XLXN_287,rotr,Qa(9),'0','0','1'); |
FDCPE_XLXN_929: FDCPE port map (XLXN_929,midiin,XLXN_929_C,'0','0',XLXN_929_CE);
XLXN_929_C <= NOT ((XLXI_277/Q0 AND XLXI_277/Q1 AND XLXI_277/Q2 AND XLXI_277/Q3)); XLXN_929_CE <= (XLXN_1072 AND NOT XLXN_1076); |
FDCPE_boardled1: FDCPE port map (boardled1,NOT datab0.PIN,boardled1_C,'0','0','1');
boardled1_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); |
datab0_I <= NOT (((NOT A1 AND NOT hex(0))
OR (A1 AND A2 AND ll1) OR (A1 AND NOT A2 AND NOT XLXN_1027))); datab0 <= datab0_I when datab0_OE = '1' else 'Z'; datab0_OE <= (NOT NAMS3 AND NOT NARE); |
datab1_I <= NOT (((NOT A1 AND NOT hex(1))
OR (A1 AND A2 AND ll2) OR (A1 AND NOT A2 AND NOT XLXN_1022))); datab1 <= datab1_I when datab1_OE = '1' else 'Z'; datab1_OE <= (NOT NAMS3 AND NOT NARE); |
datab2_I <= NOT (((NOT A1 AND NOT hex(2))
OR (A1 AND A2 AND ll3) OR (A1 AND NOT A2 AND NOT XLXN_1021))); datab2 <= datab2_I when datab2_OE = '1' else 'Z'; datab2_OE <= (NOT NAMS3 AND NOT NARE); |
datab3_I <= NOT (((NOT A1 AND NOT hex(3))
OR (A1 AND A2 AND ll4) OR (A1 AND NOT A2 AND NOT XLXN_1020))); datab3 <= datab3_I when datab3_OE = '1' else 'Z'; datab3_OE <= (NOT NAMS3 AND NOT NARE); |
datab4_I <= NOT (((NOT A1 AND NOT Qa(8))
OR (A1 AND A2 AND ll5) OR (A1 AND NOT A2 AND NOT XLXN_1028))); datab4 <= datab4_I when datab4_OE = '1' else 'Z'; datab4_OE <= (NOT NAMS3 AND NOT NARE); |
datab5_I <= NOT (((NOT A1 AND NOT butl)
OR (A1 AND A2 AND NOT XLXN_1041) OR (A1 AND NOT A2 AND NOT XLXN_1018))); datab5 <= datab5_I when datab5_OE = '1' else 'Z'; datab5_OE <= (NOT NAMS3 AND NOT NARE); |
datab6_I <= NOT (((NOT A1 AND NOT butr)
OR (A1 AND A2 AND NOT XLXN_1048) OR (A1 AND NOT A2 AND NOT XLXN_1029))); datab6 <= datab6_I when datab6_OE = '1' else 'Z'; datab6_OE <= (NOT NAMS3 AND NOT NARE); |
datab7_I <= NOT (((NOT A1 AND NOT qold)
OR (A1 AND A2 AND NOT XLXN_1049) OR (A1 AND NOT A2 AND NOT XLXN_929))); datab7 <= datab7_I when datab7_OE = '1' else 'Z'; datab7_OE <= (NOT NAMS3 AND NOT NARE); |
FDCPE_db0: FDCPE port map (db0,datab0.PIN,db0_C,'0','0','1');
db0_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); |
FDCPE_db1: FDCPE port map (db1,datab1.PIN,db1_C,'0','0','1');
db1_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); |
FDCPE_db2: FDCPE port map (db2,datab2.PIN,db2_C,'0','0','1');
db2_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); |
FDCPE_db3: FDCPE port map (db3,datab3.PIN,db3_C,'0','0','1');
db3_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); |
FDCPE_db4: FDCPE port map (db4,datab4.PIN,db4_C,'0','0','1');
db4_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); |
FDCPE_db5: FDCPE port map (db5,datab5.PIN,db5_C,'0','0','1');
db5_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); |
FDCPE_db6: FDCPE port map (db6,datab6.PIN,db6_C,'0','0','1');
db6_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); |
FDCPE_db7: FDCPE port map (db7,datab7.PIN,db7_C,'0','0','1');
db7_C <= NOT ((NOT NAWE AND NOT NAMS3 AND NOT A1)); |
FDCPE_e: FDCPE port map (e,datab1.PIN,e_C,'0','0','1');
e_C <= NOT ((NOT NAWE AND NOT NAMS3 AND A1)); |
FTCPE_hex0: FTCPE port map (hex(0),'0',N_PZ_340,NOT XLXN_268.COMB,'0','1'); |
FTCPE_hex1: FTCPE port map (hex(1),hex_T(1),N_PZ_340,NOT XLXN_268.COMB,'0','1');
hex_T(1) <= NOT (hex(0) XOR ((XLXN_268 AND NOT XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281) OR (NOT XLXN_268 AND XLXN_287 AND XLXN_280 AND XLXN_281))); |
FTCPE_hex2: FTCPE port map (hex(2),hex_T(2),N_PZ_340,NOT XLXN_268.COMB,'0','1');
hex_T(2) <= NOT ((hex(0) AND hex(1)) XOR ((hex(0) AND NOT hex(1)) OR (NOT hex(0) AND hex(1)) OR (XLXN_268 AND NOT XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281) OR (NOT XLXN_268 AND XLXN_287 AND XLXN_280 AND XLXN_281))); |
FTCPE_hex3: FTCPE port map (hex(3),hex_T(3),N_PZ_340,NOT XLXN_268.COMB,'0','1');
hex_T(3) <= (NOT hex(0) AND NOT hex(1) AND NOT hex(2)) XOR ((hex(0) AND XLXN_268 AND NOT XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281 AND hex(1) AND hex(2)) OR (hex(0) AND NOT XLXN_268 AND XLXN_287 AND XLXN_280 AND XLXN_281 AND hex(1) AND hex(2)) OR (NOT hex(0) AND XLXN_268 AND NOT XLXN_287 AND NOT XLXN_280 AND NOT XLXN_281 AND NOT hex(1) AND NOT hex(2)) OR (NOT hex(0) AND NOT XLXN_268 AND XLXN_287 AND XLXN_280 AND XLXN_281 AND NOT hex(1) AND NOT hex(2))); |
lda <= (NOT hex(0) AND hex(2))
XOR ((hex(0) AND hex(1) AND hex(3)) OR (NOT hex(1) AND hex(2) AND NOT hex(3))); |
ldb <= ((NOT hex(0) AND hex(2) AND hex(3))
OR (hex(1) AND hex(2) AND hex(3)) OR (NOT hex(0) AND hex(1) AND NOT hex(2) AND NOT hex(3))); |
ldc <= ((hex(0) AND hex(1) AND hex(2))
OR (hex(0) AND NOT hex(1) AND NOT hex(2)) OR (NOT hex(0) AND hex(1) AND NOT hex(2) AND hex(3)) OR (NOT hex(0) AND NOT hex(1) AND hex(2) AND NOT hex(3))); |
ldd <= ((hex(0) AND NOT hex(3))
OR (hex(0) AND NOT hex(1) AND NOT hex(2)) OR (NOT hex(1) AND hex(2) AND NOT hex(3))); |
lde <= (hex(0) AND NOT hex(3))
XOR ((hex(0) AND NOT hex(1) AND hex(2)) OR (NOT hex(0) AND hex(1) AND NOT hex(2) AND NOT hex(3))); |
ldf <= (hex(0) AND NOT hex(1))
XOR ((hex(0) AND NOT hex(2) AND hex(3)) OR (NOT hex(1) AND hex(2) AND NOT hex(3))); |
ldg <= ((NOT hex(1) AND NOT hex(2) AND NOT hex(3))
OR (hex(0) AND hex(1) AND hex(2) AND NOT hex(3)) OR (NOT hex(0) AND NOT hex(1) AND hex(2) AND hex(3))); |
FTCPE_ll1: FTCPE port map (ll1,'0',bl1,'0','0','1'); |
FTCPE_ll2: FTCPE port map (ll2,'0',bl2,'0','0','1'); |
FTCPE_ll3: FTCPE port map (ll3,'0',bl3,'0','0','1'); |
FTCPE_ll4: FTCPE port map (ll4,'0',bl4,'0','0','1'); |
FTCPE_ll5: FTCPE port map (ll5,'0',bl5,'0','0','1'); |
qold <= NOT ((NOT XLXN_268.COMB AND a)); |
FDCPE_rs: FDCPE port map (rs,datab0.PIN,rs_C,'0','0','1');
rs_C <= NOT ((NOT NAWE AND NOT NAMS3 AND A1)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |